1. Field of the Invention
The present invention relates to the field of data processing and more particularly to central processing units.
2. Brief Description of the Prior Art
Sparse vectors are multi-operand vectors having zero or near zero operands removed and the remaining operands packed together. An apparatus for processing such vectors by a computer's central processing unit is disclosed in U.S. Pat. No. 3,919,534 to Hutson, et al. Such apparatus forwards operands to the arithmetic logic unit (ALU) from a given sparse vector one at a time. Zero operands are provided to the ALU only when a second sparse vector being input to the ALU for coprocessing has a non-zero operand in that order. An order vector is provided for each sparse vector to indicate by the state of a bit whether the correspondingly ordered sparse vector operand is zero or non-zero.